1. Field of the Invention
The present invention relates to a memory circuit having a parity cell array, and more particularly to a memory circuit capable of a test of a real cell array and a parity cell array.
The present invention also relates to a semiconductor memory which has a memory cell array for storing parity data of write data and has a Built-in Self Test (BIST) function.
2. Description of the Related Art
One-transistor type Dynamic RAM (DRAM) is in widespread use as low-cost, high capacity memory but requires a refresh operation on account of being volatile, even in a power ON state. On the other hand, where static RAM (SRAM) is concerned, although an increase in capacity comes at a high cost, such SRAM is capable of continually holding stored data in a power ON state, meaning that it is not necessary to control a refresh operation as is the case for DRAM.
Conventionally, SRAM, which does not necessitate refresh control, has been used in mobile telephones and mobile information terminals, and the like, but the change to Broadband and links with the Internet of recent years have resulted in a need to switch to high-capacity memory, and examplifierles of DRAM being used in place of conventional SRAM have been on the increase. As a result, a need has arisen to provide DRAM that does not require refresh control from outside.
DRAM without a refresh mode of the kind described above contains a refresh control circuit that performs a refresh operation according to a predetermined cycle without the provision of refresh commands from outside. Such a refresh control circuit performs control by generating a refresh request signal according to the predetermined cycle, supplying a refresh address counter value constituting a refresh address to a decoder, and sequentially refreshing internal memory with respect to this predetermined cycle. Here, when there is a conflict between a read command from outside and a refresh request generated internally, a refresh operation must be performed in response to the internal refresh request while the read request from outside is being received.
In order to make the above operation possible, the present applicant has developed a memory which is provided with a parity cell array in addition to a real cell array; which computes and stores to the parity cell array a parity bit from data written to the real cell array; and recovers, with respect to the parity bit, data which has not been read out as a result of prioritizing an internal refresh request generated at the time of a read request.
However, with the DRAM described above, when data of the real cell array is read, data of the real cell array may sometimes be partially corrected by a parity bit which is read out from a parity cell array. Consequently, there is the problem that it is not possible to suitably perform an operational test prior to shipment.
In other words, since a parity cell array is installed in order to recover data from a real cell array by means of a parity bit, during an operational test it is not possible to judge from data outputted to data input/output terminals whether or not read and write operations of the real cell array are normal. Furthermore, the data of the parity cell array is only utilized in internal data recovery, that is, a circuit for external readout is not provided. It is therefore not possible to also judge whether or not the parity cell array can be read or written to normally.
Such a problem is not limited to DRAM for which there is no refresh mode. There are also similar problems with memory configured to recover a defective bit, by means of internal circuitry, using a parity bit or other such error correction code (“ECC” hereinafter).
Further, the size of the wafer in which the semiconductor memory is formed tends to be large in order to reduce the manufacturing costs for semiconductor memory. As a result of making the wafer size large, the number of semiconductor memory chips formed on the wafer increases, as does the test time per wafer. Consequently, Built-in Self Test (BIST) technology, which involves the installation of a test circuit in the semiconductor memory and shortens the test time, has been developed.
In a Built-in Self Test, at the time of a test mode, the test circuit generates a test pattern (write address, write data). Then, in accordance with this test pattern, the test circuit writes data to memory cells, and then compares data read out from the memory cells with expected values to thereby confirm that the semiconductor memory is operating correctly. Then, the test pattern is supplied to nodes being close to external terminals in order to test the signal paths for address and data employed in a normal operation.
FIG. 19 shows an overview of a DRAM operating as an SRAM. In the figure, signal lines indicated by bold lines are formed in a plurality. The DRAM has an address buffer 110, a data input/output buffer 122, a parity generating circuit 124, a parity test circuit 142, a plurality of real cell arrays RCA, and a parity cell array PCA.
The real cell arrays RCA are each formed so as to correspond with data input/output terminals DQ. The parity cell array PCA stores parity data for data which is stored in the real cell arrays RCA. A refresh operation is executed in accordance with a refresh request outputted by a timer (not shown) contained in the DRAM.
The parity generating circuit 124 generates parity data for write data during a write operation, and writes such parity data to the parity cell array PCA. Further, write data supplied via the data input/output terminal DQ are written directly to the real cell arrays RCA.
Memory cell refresh operations are executed sequentially for each of the memory cell arrays RCA, PCA. When there is a conflict between a refresh operation and a write operation, these operations are executed sequentially starting with the operation request which is received first.
When a readout operation is requested while executing a refresh operation for any of the real cell arrays RCA, the parity test circuit 142 recovers data, which has been stored in the real cell array RCA undergoing a refresh operation, on the basis of data read out from a real cell array RCA for which a refresh operation has not been executed and from the parity cell array PCA.
When Built-in Self Test technology is adopted for DRAM having the above-described parity cell array PCA, it is desirable that, similarly to general DRAM, the test pattern (data) generated by the test circuit be supplied to a data input/output buffer 122. Meanwhile, a data bus line connected to the parity cell array PCA is connected with the data input/output buffer 122 via the parity generating circuit 124 or the parity test circuit 142. For this reason, with conventional Self Test technology, the test pattern generated by the test circuit cannot be directly supplied to the data bus line connected with the parity cell array PCA. Thus, it has not been possible to test DRAM having a parity cell array PCA by means of a Built-in Self Test.